AN UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1 Decoder

被引：0

作者：

Zummach, Eduardo ^{[1
]}

Palau, Roberta ^{[1
,2
]}

Goebel, Jones ^{[1
,2
]}

Sampaio, Felipe ^{[3
]}

Correa, Guilherme ^{[1
,2
]}

Agostini, Luciano ^{[1
,2
]}

Porto, Marcelo ^{[1
,2
]}

机构：

[1] Fed Univ Pelotas UFPel, Video Technol Res Grp ViTech, Pelotas, RS, Brazil

[2] Fed Univ Pelotas UFPel, Grad Program Comp PPGC, Pelotas, RS, Brazil

[3] Fed Inst Rio Grande do Sul IFRS, Farroupilha, Brazil

来源：

2020 27TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2020年

关键词：

AV1; In-loop filter; Deblocking Filter; Hardware Design; Video Coding;

D O I：

10.1109/icecs49266.2020.9294930

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a hardware design for the Deblocking Filter (DBF) in the AOM Video 1 (AV1) decoder. The DBF is the first filter of the AV1 encoding loop, being used to attenuate blocking artifacts and to improve the subjective video quality. The presented hardware design is capable to process up to 56 samples per clock cycle, aiming at processing Ultra-High Definition (UHD) videos with 4098x2160 pixels (4K) at 60 frames per second when running at 16.2 MHz. The architecture was synthesized to ASIC using the 40nm TSMC library, requiring 39.35K gates and with a power dissipation of 3.96 mW. At the best of the authors' knowledge, this is the first hardware design targeting the AV1 DBF presented in the literature.

引用

页数：4