Implementation of Givens QR-decomposition in FPGA

被引：0

作者：

Sergyienko, A ^{[1
]}

Maslennikov, O

机构：

[1] Natl Tech Univ Ukraine, Dept Comp Sci, Kiev, Ukraine

[2] Tech Univ Koszalin, Koszalin, Poland

来源：

PARALLEL PROCESSING APPLIED MATHEMATICS | 2002年 / 2328卷

关键词：

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

A new parallel processor structure for Givens QR-decomposition intended for the FPGA implementation is presented. The structure is derived using method of mapping regular algorithms using affine transformations of the algorithm graph. The method supports pipelined processor unit design, and provides efficient hardware utilization. An example of the implementation of this structure in the Xilinx Virtex FPGA devices is presented.

引用

页码：458 / 465

页数：8

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