Harmonic fold back reduction at the N-path filters

In this paper, a method is proposed to reduce harmonic fold back (HFB) problem of N-path filters, without increasing the input reference clock (f(CLK)) frequency. The HFB at the N-path filter is analyzed, and simple expressions are extracted to model this problem. Using the results of the analysis, an M-of-N-path filter has been proposed that behaves like an MxN-path filter in terms of HFB problem; however, the f(CLK) frequency of this structure is the same as an N-path filter. To demonstrate the feasibility of the proposed idea, a 3-of-4-path filter is designed, and its characteristics are compared with 4-path and 12-path filters by simulation. Impacts of different non-idealities like clock-phase error, mismatch, and parasitic capacitance are investigated. The transistor-level implementation of this filter is performed in 0.18 mu m Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results show that the filter has the pass-band gain of 17dB, tuning range of 0.2-1.2GHz, -3dB bandwidth of 25MHz, quality factor of 8-48, 18dB out-of-band rejection, 16dB rejection of the third harmonic of switching frequency (f(s)), and the noise figure of 4.35dB (using ideal G(m) cells) and 6.95dB (for practical G(m) cells). The strongest harmonic folding to the filter pass-band occurs around 11f(s) with the attenuation of 23.8dB. Each G(m) cell draws about 12.4mA from 1.8V supply, and the out-of-band IIP3 and P-1dB,P-CP are 17 and 4dBm, respectively. Copyright (c) 2016 John Wiley & Sons, Ltd.