Suppression of floating body effects by controlling potential profile in the lower body region of silicon-on-insulator metal-oxide-semiconductor field effect transistors

This paper describes a promising way to suppress floating body effects (FBE) in fully depleted (FD) silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI MOSFETs), which is applicable to the complementary MOS (CMOS) structure. The FEE is suppressed by controlling the potential profile by supplying an adequate positive substrate voltage (V-SUB). FD SOI NMOSFETs show a strong dependence of V-T on V-D in the higher V-D range, which is induced by the FBE. The accumulation in the body of holes generated through impact ionization raises the body potential, and hence lowers V-T. A positive V-SUB improves the anomalous subthreshold slope,and thereby weakens the dependence of V-T on V-D. This is mainly because the positive V-SUB lowers the potential barrier height for holes in the lower body region, which enhances the flow of holes in the body into the source, and thus suppresses the increase in body potential. The decrease in the potential barrier height for holes is supported by two-dimensional device simulation. Supplying a positive V-SUB causes hardly any changes in the characteristics of SOI P-channel MOSFETs (PMOSFETs). Therefore, supplying a positive voltage to the substrate is useful for the SOI CMOS structure.