Ultra-Low Power Hybrid Full Adder Circuit for Digital Signal Processing and Biomedical Applications

被引：0
|
作者：
Singh, Anil [1 ]
Upadhyay, Rahul Mani [1 ]
Kumar, Manish [1 ]
机构：
[1] Madan Mohan Malaviya Univ Technol, Dept ECE, Gorakhpur, Uttar Pradesh, India
来源：
JOURNAL OF ACTIVE AND PASSIVE ELECTRONIC DEVICES | 2020年 / 15卷 / 3-4期
关键词：
Full adder; power; hybrid adder; ultra-low power; PERFORMANCE ANALYSIS; HIGH-SPEED; CMOS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An ultra-low power 1-bit full adder circuit is proposed in this paper. This circuit consists of three modules that work in integration with each other to generate the output. Module 1 performs the XOR-XNOR operation while module 2 performs the XOR operation and produces the SUM output. Module 3 is a multiplexer circuit that gives the Carry out (C-out) of the adder circuit. The power dissipation of the proposed full adder outperformed with some of previously reported works. The circuit is designed and simulated by using Mentor Graphics simulation tool in 180nm TSMC technology.
引用
收藏
页码：295 / 308
页数：14
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