Development of fault-tolerant MLI topology

被引：35

作者：

Jalhotra, Manik ^{[1
]}

Kumar, Lalit ^{[1
]}

Gautam, Shivam Prakash ^{[2
]}

Gupta, Shubhrata ^{[1
]}

机构：

[1] NIT Raipur, Dept Elect Engn, Raipur, Madhya Pradesh, India

[2] Indian Inst Technol, Dept Elect Engn, Bombay, Maharashtra, India

来源：

IET POWER ELECTRONICS | 2018年 / 11卷 / 08期

关键词：

capacitors; fault tolerance; invertors; lesser device count; fault-tolerant MLI topology; multilevel inverters; MLIs; deep roots; industrial sectors; two-level inverters; semiconductor devices; novel fault-tolerant topology; multiswitch faults; CONVERTER-BASED STATCOM; CLAMPED CONVERTER; INVERTER; RELIABILITY; CAPABILITY; STRATEGY; DESIGN;

D O I：

10.1049/iet-pel.2017.0683

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Multilevel inverters (MLIs) have developed deep roots in various industrial sectors owing to their advantages over conventional two-level inverters. However, the reliability of the semiconductor devices has been one of the major concerns for the proper functioning of MLI. Therefore, a novel fault-tolerant topology is proposed in this study. The proposed topology is capable to tolerate single- and multi-switch faults. It has lesser device count compared with the most recent work in the field. Moreover, it achieves inherent voltage balancing across capacitors. The proposed fault-tolerant topology is simulated in MATLAB/Simulink and validated experimentally.

引用

页码：1416 / 1424

页数：9

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