<bold>An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization</bold>

被引：0
|
作者：
Saif, Sherif M. [1 ]
Abbas, Hazern M. [1 ]
Nassar, Salwa M. [2 ]
机构：
[1] Mentor Graph Corp, 51 Beirut St, Cairo 11341, Egypt
[2] Elect Res Inst, Giza, Egypt
来源：
2006 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORK PROCEEDINGS, VOLS 1-10 | 2006年
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D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents a Field Programmable Gate Array (FPGA) implementation for a Competitive Hopfield Neural Network (CHNN) to be used in image histogram equalization (HE). This algorithm is so computationally expensive that a viable hardware implementation is appealing provided that an efficient algorithm-to-architecture mapping can be achieved. The Xilinx Virtex-E was used for the hardware realization. An efficient use of the chip is outlined in the results.
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页码：2815 / +
页数：3
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