FPGA based SHEPWM Switching Scheme for Single Phase Cascaded H-Bridge Multi-Level Inverter

The aim of the present work is to develop and realize an appropriate switching scheme for different levels of multi-level inverter (MLI) with an intention to reduce the level of harmonics. Selective harmonie elimination pulsewidth modulation (SHEPWM) switching scheme is implemented using field programmable gate array (FPGA) which is an effective digital controller for power electronic applications. FPGAs also provide extensive flexibility in change of bit-widths and parallel processing at instructionlevel. The proposed switching sehe me is tested with the developed experimental set-up consisting of a set of five H-bridge inverters containing twenty switches (for 11-level) that are switched using the pulses generated from FPGA. The experimental results for different levels of inverter with resistive load are reported along with the percentage total harmonie distortion (% THD) values and are compared with the theoretical calculation.