A 16-bit High-Speed Low-Power Hybrid Adder

This paper presents the architecture of a hybrid adder based on the combination of the carry-lookahead and carry-select adder architectures. A 16-bit adder is designed as a case study to show the efficiency of the proposed architecture. This adder is implemented in a 0.18 mu m CMOS technology using domino logic for most of the sub-circuits. The simulation results show that the 16-bit hybrid adder achieves a worst-case delay of 876.7 ps and has an average power consumption of 787.2 mu W at 125 degrees C for a throughput of 100 Mega operations per second in the slow-slow corner. The paper also demonstrates the efficiency of this architecture for higher number of bits.