Equivalence Checking of Reversible Circuits

Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits' primary inputs and outputs must be in pure logic states but the circuits may include elementary quantum gates in addition to reversible logic gates. The specification can include don't-cares arising front constant inputs, garbage outputs, and total or partial don't-cares in the underlying target junction. The paper explores well-known techniques front irreversible equivalence checking and how they can be applied in the domain of reversible circuits. Two approaches are considered. The first employs decision diagram techniques and the second uses Boolean satisfiability. Experimental results show that for both methods, circuits with up to 27,000 gates, as well as adders with more than 100 inputs and outputs, are handled in under three minutes with reasonable memory requirements.