Modeling and Parameter Extraction of CMOS On-Chip Spiral Inductors With Ground Shields

被引:11
|
作者
Ding, Bowen [1 ,2 ]
Yuan, Shengyue [1 ]
Zhao, Chen [1 ,2 ]
Tian, Tong [1 ]
机构
[1] Chinese Acad Sci, Sci & Technol Microsyst Lab, Shanghai Inst Microsyst & Informat Technol, Shanghai 200050, Peoples R China
[2] Univ Chinese Acad Sci, Beijing 100049, Peoples R China
关键词
CMOS; ground shield structure; inductor model; parameter extraction;
D O I
10.1109/LMWC.2017.2691059
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new simple p-equivalent model with parameter extraction method is presented in this letter, to develop accurate models for spiral inductors on low-resistance CMOS substrate with ground shield structure. C-L-R network is introduced to model the ground loop in the lower metal strips, replacing the conventional C-R-C network. This model contains only ten frequency-independent components with explicit physical meaning, which has fewer elements and is easy to be extracted. Frequency responses of the extracted results are in excellent agreement with the measurements and EM simulations of inductors with different ground shields and layout designs up to 40 GHz. This proves the validity of the proposed model and parameter extraction method. Finally, extracted results of the inductors with different ground shields are compared and investigated.
引用
收藏
页码:431 / 433
页数:3
相关论文
共 50 条
  • [41] MODELING OF CURRENT CROWDING FOR ON-CHIP MULTI TURN DIFFERENTIAL -SPIRAL INDUCTORS
    Lin, Changgui
    Kalkur, T. S.
    EUROCON 2009: INTERNATIONAL IEEE CONFERENCE DEVOTED TO THE 150 ANNIVERSARY OF ALEXANDER S. POPOV, VOLS 1- 4, PROCEEDINGS, 2009, : 178 - 182
  • [42] Neural network-based modeling & design of on-chip spiral inductors
    Ilumoka, A
    Park, YB
    PROCEEDINGS OF THE THIRTY-SIXTH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY, 2004, : 561 - 564
  • [43] Electrical Modeling and Characterization of Graphene-Based On-Chip Spiral Inductors
    Wang, Da-Wei
    Yuan, Meng-Jiao
    Dai, Jia-Yun
    Zhao, Wen-Sheng
    MICROMACHINES, 2022, 13 (11)
  • [44] Enhancement of broadband performance for on-chip spiral inductors with inner-patterned-ground
    Shi, Jinglin
    Sun, Sheng
    Xiong, Yong Zhong
    Yeoh, Wooi Gan
    Yeo, Kiat Seng
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2008, 50 (07) : 1744 - 1746
  • [45] Performance trends of on-chip spiral inductors for RFICs
    Pan, Shu Jun
    Li, Le-Wei
    Yin, Wen-Yan
    Progress in Electromagnetics Research, 2004, 45 : 123 - 151
  • [46] Design optimization methodology for on-chip spiral inductors
    Okada, K
    Hoshino, H
    Onodera, H
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (06) : 933 - 941
  • [47] A Study of On-Chip Stacked Multiloop Spiral Inductors
    Yang, Kai
    Yin, Wen-Yan
    Shi, Jinglin
    Kang, Kai
    Mao, Jun-Fa
    Zhang, Y. P.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (11) : 3236 - 3245
  • [48] Comparative Analysis of various On-Chip Spiral Inductors
    Beryl, R.
    Vaithianathan, V.
    Kirubaveni, S.
    2013 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2013, : 437 - 441
  • [49] A simple model parameter extraction methodology for an on-chip spiral inductor
    Oh, NJ
    Lee, SG
    ETRI JOURNAL, 2006, 28 (01) : 115 - 118
  • [50] A novel analytical approach to parameter extraction for on-chip spiral inductors taking into account high-order parasitic effect
    Huang, F. Y.
    Lu, J. X.
    Jiang, D. M.
    Wang, X. C.
    Jiang, N.
    SOLID-STATE ELECTRONICS, 2006, 50 (9-10) : 1557 - 1562