A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS

被引:0
|
作者
Xuan-Thuan Nguyen [1 ]
Trong-Thuc Hoang [2 ]
Inoue, Katsumi [2 ]
Ngoc-Tu Bui [2 ]
Van-Phuc Hoang [3 ]
Cong-Kha Pham [2 ]
机构
[1] Univ Toronto, 40 St George St, Toronto, ON M5S 3H7, Canada
[2] Univ Electrocommun, 1-5-1 Chofugaoka, Chofu, Tokyo 1828585, Japan
[3] Le Quy Don Tech Univ, 236 Hoang Quoc Viet St, Hanoi, Vietnam
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Although bitmap index (BI) can surmount complex and multi-dimensional queries, the creation of BI itself is a time-consuming task. Many studies exploit the highly parallel processing capabilities of multi-core CPUs, graphics processing units (GPUs), or field-programmable gate arrays (FPGAs) to overcome this obstacle. This study, on the other hand, proposes a 65-nm silicon-on-thin-buried-oxide (SOTB) hardware accelerator dedicated to BI creation. The fabricated chip could operate at different supply voltages, from 0.45-V to 1.2-V. Concretely, in the active mode with the supply voltage of 1.2-V, this chip was fully operational at 90-MHz and consumed approximately 88.1pJ/cycle. In the standby mode with the supply voltage of 0.45V and clock gated, the power consumption was only 476.1-nW. Moreover, when the reverse back-gate bias voltage of -2.5-V is supplied, the standby power sharply dropped to 0.27-nW or approximately 1,763 times. This achievement is vitally essential for the energy-efficient applications, where the performance should be maximized during peak workload hours and the power should be minimized during off-peak time.
引用
收藏
页数:4
相关论文
共 10 条
  • [1] A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB
    Xuan-Thuan Nguyen
    Trong-Thuc Hoang
    Hong-Thu Nguyen
    Inoue, Katsumi
    Cong-Kha Pham
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2019, 69 : 112 - 117
  • [2] A 65 nm 1.0 v 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT
    [J]. 1600, Institute of Electrical and Electronics Engineers Inc., United States (00):
  • [3] A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) Embedded SRAM with 13.72 nW/Mbit Standby Power for Smart IoT
    Yabuuchi, Makoto
    Nii, Koji
    Tanaka, Shinji
    Shinozaki, Yoshihiro
    Yamamoto, Yoshiki
    Hasegawa, Takumi
    Shinkawata, Hiroki
    Kamohara, Shiro
    [J]. 2017 SYMPOSIUM ON VLSI TECHNOLOGY, 2017, : C220 - C221
  • [4] A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) Embedded SRAM with 13.72 nW/Mbit Standby Power for Smart IoT
    Yabuuchi, Makoto
    Nii, Koji
    Tanaka, Shinji
    Shinozaki, Yoshihiro
    Yamamoto, Yoshiki
    Hasegawa, Takumi
    Shinkawata, Hiroki
    Kamohara, Shiro
    [J]. 2017 SYMPOSIUM ON VLSI CIRCUITS, 2017, : C220 - C221
  • [5] An Implementation of Ultra-Low-Standby Power SRAMs using 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT
    Nii, Koji
    [J]. PROCEEDINGS OF 2017 7TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS, DESIGN, AND VERIFICATION (ICDV), 2017, : 9 - 9
  • [6] Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)
    Hoang, Trong-Thuc
    Duran, Ckristian
    Nguyen, Khai-Duy
    Dang, Tuan-Kiet
    Nhu, Quynh Nguyen Quang
    Than, Phuc Hong
    Tran, Xuan-Tu
    Le, Duc-Hung
    Tsukamoto, Akira
    Suzaki, Kuniyasu
    Pham, Cong-Kha
    [J]. IEICE ELECTRONICS EXPRESS, 2020, 17 (20):
  • [7] Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)
    University of Electro-Communications , Tokyo
    182-8585, Japan
    不详
    135-0064, Japan
    不详
    不详
    不详
    不详
    不详
    135-0064, Japan
    [J]. IEICE Electron. Express, 2020, 20 (1-6): : 1 - 6
  • [8] Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias
    Trong-Thuc Hoang
    Xuan-Thuan Nguyen
    Duc-Hung Le
    Cong-Kha Pham
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019, 66 (10) : 1723 - 1727
  • [9] A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS
    Xuan-Thuan Nguyen
    Trong-Thuc Hoang
    Hong-Thu Nguyen
    Inoue, Katsumi
    Pham, Cong-Kha
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2020, 73
  • [10] Ultra-Low-Standby Power 6T Single-port and 8T Dual-port SRAMs on 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT Applications
    Nii, Koji
    Yabuuchi, Makoto
    Sawada, Yohei
    Tanaka, Shinji
    Shinozaki, Yoshihiro
    Ito, Kyoji
    Umemoto, Yukiko
    Yamamoto, Yoshiki
    Hasegawa, Takumi
    Shinkawata, Hiroki
    Kamohara, Shiro
    [J]. 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1171 - 1174