A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) Embedded SRAM with 13.72 nW/Mbit Standby Power for Smart IoT

被引:0
|
作者
Yabuuchi, Makoto [1 ]
Nii, Koji [1 ]
Tanaka, Shinji [1 ]
Shinozaki, Yoshihiro [2 ]
Yamamoto, Yoshiki [1 ]
Hasegawa, Takumi [1 ]
Shinkawata, Hiroki [1 ]
Kamohara, Shiro [1 ]
机构
[1] Renesas Elect Corp, Tokyo 1878588, Japan
[2] Nippon Systemware Co Ltd, Tokyo 1508577, Japan
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A 65-nm Silicon-on-Thin-Box (SOTB) embedded SRAM is demonstrated. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.84 ns at 1.0 V overdrive and 25 degrees C, which is improved by 60% and thus we achieved over 380 MHz operation. Up to 20% active read power reduction is also achieved by using proposed localized adoptive wordline width control.
引用
收藏
页码:C220 / C221
页数:2
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