Low-power CMOS analog front-end for wireless communication

被引：1

作者：

Taha, AA ^{[1
]}

Abo-El-Soud, MA ^{[1
]}

AbedRassoul, RA ^{[1
]}

Farrag, AK ^{[1
]}

机构：

[1] Mansoura Univ, Fac Engn, Elect & Comm Eng Dept, Mansoura, Egypt

来源：

2002 IEEE PROCEEDINGS OF THE NINETEENTH NATIONAL RADIO SCIENCE CONFERENCE, VOLS 1 AND 2 | 2002年

关键词：

D O I：

10.1109/NRSC.2002.1022656

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-voltage low-power CMOS VLSI circuit for the main part of an analog front-end has been designed for wireless communication systems. Such analog circuits include an antialiasing filter, sample and hold circuit, and sixth order switched-resistor (SR) low-pass filter. The sample and hold circuit and the SR low-pass filter operate at 300 kHz. The effects of feedthrough and dynamic range in these circuits are taken into account. The proposed circuits are realized in a standard 0.35 pm CMOS technology. The architecture and circuits described in this paper consumes about 3 muW from a +/-1 V power supply.

引用

页码：467 / 474

页数：8

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