A 0.25 μm 700 V BCD Technology with Ultra-low Specific On-resistance SJ-LDMOS

In this paper, a 0.25 mu m 700 V Bipolar-CMOS-DMOS (BCD) process platform is reported, which integrates the super junction lateral double-diffused metal-oxide semiconductor (SJ-LDMOS) with ultra-low specific onresistance R-on,R-sp. The SJ-LDMOS features the SJ pillars in the bulk of the drift region, introducing a low resistance current path in the on-state and decreasing the R-on,R-sp. By optimizing the charge balance among the N- drift region, PN pillars and Psubstrate, the proposed SJ-LDMOS can be used at 500 V, 650 V and 700 V voltage levels with the experimental breakdown voltage VB of 605 V, 745 V and 790 V. The corresponding R-on,R-sp is 3.3 Omega.mm(2), 5.8 Omega.mm(2) and 7.1 Omega.mm(2), respectively. The measured Ron, sp is 45.5% lower than the theoretical limit of the triple RESURF technology under the same V-B. This SJ-based 700V BCD technology also provides other variable integrated devices: 700 V nJFET; 30 V / 15 V / 7.5 V CMOS; 20 V NPN and PNP; and poly resistor.