An improved VLSI implementation method of FFT processor

被引：0

作者：

Liu, Guihua ^{[1
,2
]}

Feng, Quanyuan ^{[1
]}

机构：

[1] SouthWest Jiaotong Univ, Inst Microelect, Chengdu 610031, Peoples R China

[2] Southwest Univ Sci & Technol, Mianyang Sichuan 621010, Peoples R China

来源：

2006 8TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, VOLS 1-4 | 2006年

基金：

美国国家科学基金会;

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An improved VLSI realization of a 1024-dot pipeline FFT processor for handling high speed digital signal has been presented by optimizing the pipeline of complex multiplication and the generation of twiddle factor The method based on CORDIC algorithm is adopted to achieve a real-time FFT processor and results in a substantial savings in hardware resources and the amount of delay elements. It is easily implemented in hardware. The processor has been successful v applied to a Xilinx Virtex-IIxc2v500 chip and obtains the operating clock frequency at 132MHz.

引用

页码：131 / +

页数：2

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