High-voltage stress test paradigms of analog CMOS ICs for gate-oxide reliability enhancement

被引：12

作者：

Khalil, MA ^{[1
]}

Wey, CL ^{[1
]}

机构：

[1] Michigan State Univ, Dept Elect & Comp Engn, E Lansing, MI 48824 USA

来源：

19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/VTS.2001.923458

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents the first-ever research on high-voltage stress of analog circuits to enhance their oxide reliability and to reduce the manufacturing cost, The emphasis of this paper is placed on how to properly stress analog circuits and the development of efficient algorithms for generating stress vectors that meet the stress coverage requirement within a feasible stress time.

引用

页码：333 / 338

页数：6

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