A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

被引:234
|
作者
Yamaoka, Masanao [1 ]
Yoshimura, Chihiro [1 ]
Hayashi, Masato [1 ]
Okuyama, Takuya [1 ]
Aoki, Hidetaka [2 ]
Mizuno, Hiroyuki [3 ]
机构
[1] Hitachi Ltd, Res & Dev Grp, Kokubunji, Tokyo 1858601, Japan
[2] Hitachi Ltd, Res & Dev Grp, Yokohama, Kanagawa 2440817, Japan
[3] Hitachi Ltd, Management Planning Off, Chiyoda Ku, Tokyo 1008220, Japan
关键词
CMOS annealing; combinatorial optimization problem; Ising computing; Ising model; natural computing; SRAM; variation;
D O I
10.1109/JSSC.2015.2498601
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the behavior of magnetic spins, and solves combinatorial optimization problems efficiently exploiting its intrinsic convergence properties. In the computing, "CMOS annealing" is used to find a better solution for the problems. A 20k-spin prototype Ising chip is fabricated in 65 nm process. The Ising chip achieves 100 MHz operation and its capability of solving combinatorial optimization problems using an Ising model is confirmed. The power efficiency of the chip can be estimated to be 1800 times higher than that of a general purpose CPU when running an approximation algorithm.
引用
收藏
页码:303 / 309
页数:7
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