Brain-inspired ferroelectric Si nanowire synaptic device

被引:17
|
作者
Lee, M. [1 ]
Park, W. [2 ]
Son, H. [3 ]
Seo, J. [1 ]
Kwon, O. [2 ]
Oh, S. [2 ]
Hahm, M. G. [1 ]
Kim, U. J. [4 ]
Cho, B. [2 ]
机构
[1] Inha Univ, Dept Mat Sci & Engn, 100 Inha Ro, Incheon 22212, South Korea
[2] Chungbuk Natl Univ, Dept Adv Mat Engn, 1 Chungdae Ro, Cheongju 28644, Chungbuk, South Korea
[3] Chung Ang Univ, Sch Integrat Engn, Seoul 06974, South Korea
[4] Samsung Adv Inst Technol, Imaging Device Lab, Suwon 443803, South Korea
来源
APL MATERIALS | 2021年 / 9卷 / 03期
基金
新加坡国家研究基金会;
关键词
Behavioral research - Computer software - Energy efficiency - Field programmable gate arrays (FPGA) - Field effect transistors - Computer circuits - Pattern recognition - Silicon - Brain - Computation theory - Ferroelectricity - Fluorine compounds;
D O I
10.1063/5.0035220
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
We herein demonstrate a brain-inspired synaptic device using a poly(vinylidene fluoride) and trifluoroethylene (PVDF-TrFE)/silicon nanowire (Si NW) based ferroelectric field effect transistor (FeFET). The PVDF-TrFE/Si NW FeFET structure achieves reliable synaptic plasticity such as symmetrical potentiation and depression, thanks to the reversible dynamics of the PVDF-TrFE permanent dipole moment. The calculated asymmetric ratio of potentiation and depression is as low as 0.41 at the optimized bias condition, indicating a symmetrical synaptic plasticity behavior. Pattern recognition accuracy based on the actual synaptic plasticity data of the synaptic device can be estimated via the CrossSim simulation software. Our simulation result reveals a high pattern recognition accuracy of 85.1%, showing a potential feasibility for neuromorphic systems. Furthermore, the inverter-in-synapse transistor consisting of the Si NW FeFET synapse and resistor connected in series is able to provide energy-efficient logic circuits. A total noise margin [(NMH + NML)/V-DD] of 41.6% is achieved, and the power consumption [P-s = V-DD(I-D,I-L + I-D,I-H)/2] of the logic-in-synapse transistor is evaluated to be 0.6 mu W per logic gate. This study would shed light on the way toward a brain-inspired neuromorphic computing system based on the FeFET synapse device.
引用
收藏
页数:6
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