共 50 条
- [31] Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level [J]. ARCHITECTURE OF COMPUTING SYSTEMS, ARCS 2024, 2024, 14842 : 237 - 249
- [32] Incorporating area-time flexibility to a Binary Signed-Digit adder [J]. APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2002, : 485 - 489
- [34] Design and synthesis of a carry-free signed-digit decimal adder [J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 1089 - 1092
- [35] Compact signed-digit adder using multiple-valued logic [J]. SEVENTEENTH CONFERENCE ON ADVANCED RESEARCH IN VLSI, PROCEEDINGS, 1997, : 96 - 113
- [36] Optical binary logic gate-based modified signed-digit arithmetic [J]. OPTICS AND LASER TECHNOLOGY, 2002, 34 (07): : 501 - 508
- [37] MODIFIED SIGNED-DIGIT OPTICAL PROCESSORS USING COMPUTER-GENERATED HOLOGRAMS [J]. APPLIED OPTICS, 1992, 31 (29): : 6193 - 6199
- [38] OPTOELECTRONIC BUTTERFLY INTERCONNECTION ARCHITECTURE OF MODIFIED SIGNED-DIGIT ARITHMETIC SYSTEMS - FULLY PARALLEL ADDER AND SUBTRACTER [J]. APPLIED OPTICS, 1994, 33 (29): : 6755 - 6761
- [39] Quaternary signed-digit arithmetic operations for optical computing [J]. PHOTONIC DEVICES AND ALGORITHMS FOR COMPUTING, 1999, 3805 : 258 - 263