A digital-calibration technique for redundant radix-4 pipelined analog-to-digital converters

被引：5
|
作者：
Furuta, Masanori [1 ]
Kawahito, Shoji [1 ]
Miyazaki, Daisuke [1 ]
机构：
[1] Shizuoka Univ, Res Inst Elect, Hamamatsu, Shizuoka 4328011, Japan
来源：
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT | 2007年 / 56卷 / 06期
关键词：
capacitor mismatch; digital calibration; error measurement; pipelined analog-to-digital converter (ADC);
D O I：
10.1109/TIM.2007.904569
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a digital-calibration technique, which corrects gain errors due to capacitor mismatch and offset errors due to charge injection in redundant radix- 4 pipelined analog-to-digital converters (ADCs). The error coefficients are directly measured using an integral nonlinearity (INL) plot. The proposed method simplifies the error-measurement process and removes on-chip measurement circuits in the ADC. Computer simulations show that the maximum INL of 15 LSB in an uncalibrated 15-bit ADC is reduced to less than 0.3 LSB using the digital calibration.
引用
收藏
页码：2301 / 2311
页数：11
相关论文
共 50 条
  • [1] Analysis of INL in radix-4 pipelined analog-to-digital converters
    Farshidi, E.
    Rahmani, N.
    [J]. International Journal of Engineering, Transactions A: Basics, 2015, 28 (04): : 560 - 569
  • [2] Analysis of Integral Nonlinearity in Radix-4 Pipelined Analog-to-Digital Converters
    Farshidi, E.
    Rahmani, N.
    [J]. INTERNATIONAL JOURNAL OF ENGINEERING, 2015, 28 (04): : 546 - 552
  • [3] A digital calibration technique for pipelined analog-to-digital converters
    Furuta, M
    Kawahito, S
    Miyazaki, D
    [J]. IMTC 2002: PROCEEDINGS OF THE 19TH IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1 & 2, 2002, : 713 - 717
  • [4] Digital background calibration technique for pipelined analog-to-digital converters
    Liu, HC
    Lee, ZM
    Wu, JT
    [J]. PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING, 2003, : 881 - 884
  • [5] A digital calibration technique of capacitor mismatch for pipelined analog-to-digital converters
    Masanori, Furuta
    Shoji, Kawahito
    Daisuke, Miyazaki
    [J]. IEICE Transactions on Electronics, 2002, E85-C (08) : 1562 - 1568
  • [6] A digital calibration technique of capacitor mismatch for pipelined analog-to-digital converters
    Furuta, M
    Kawahito, S
    Miyazaki, D
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2002, E85C (08): : 1562 - 1568
  • [7] An adaptive digital domain calibration technique for pipelined analog-to-digital converters
    Hedayati, H
    Kashmiri, SM
    Shoaei, O
    [J]. ICM 2003: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2003, : 219 - 222
  • [8] A digital calibration technique of pipelined analog-to-digital converter
    School of Electronics and Information Engineering, Xi'an Jiaotong University, Xi'an 710049, China
    [J]. Hsi An Chiao Tung Ta Hsueh, 2008, 8 (991-995):
  • [9] Digital background calibration for memory effects in pipelined analog-to-digital converters
    Keane, JP
    Hurst, PJ
    Lewis, SH
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (03) : 511 - 525
  • [10] An incomplete settling technique for pipelined analog-to-digital converters
    Li, Fule
    Wang, Zhihua
    Li, Dongmei
    [J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 3590 - +
12345