Deep Learning Accelerator on FPGA Using Handwritten Digit Recognition for Example

被引：0

作者：

Vo Thanh Phat ^{[1
]}

Pham Huu Tho ^{[1
]}

Ha Binh Dat ^{[1
]}

Chou, Chung-Han ^{[2
]}

机构：

[1] Ton Duc Thang Univ, Ho Chi Minh City, Vietnam

[2] FengChia Univ, Taichung, Taiwan

来源：

2018 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-TAIWAN (ICCE-TW) | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an edge inference accelerator for deep learning application "Handwriting recognition" using field programmable gate array (FPGA). The parameter of the neuron network is trained using GPU and then download to an off-chip DRAM for the accelerator to access. The image data is transfered through Bluetooth from smart phone to the deep learning accelerator. This accelerator architecture can fit any neuron network and is suitable for consumer electronics such as IoT applications.

引用

页数：2

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