Architecture-level performance estimation for IP-based embedded systems

被引:1
|
作者
Ueda, K [1 ]
Sakanushi, K [1 ]
Takeuchi, Y [1 ]
Imai, M [1 ]
机构
[1] Osaka Univ, Grad Sch Informat Sci & Technol, Suita, Osaka 565, Japan
关键词
D O I
10.1109/DATE.2004.1269024
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper we propose a architecture-level performance estimation method for IP-based embedded systems using system-level profiling. Our method enables the performance estimation by the following procedures; 1) System-level profiling. 2) Automatic construction of the execution dependency graph (EDG) from the profile information. 3) Estimation of the system performance based on the EDG analysis. Our method enables fast performance estimation because it can estimate the performance of various architectures from the same system-level profile information. Experimental results show that our estimation method is about 10,000 times faster than the architecture-level simulations.
引用
收藏
页码:1002 / 1007
页数:6
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