A low-power relaxation oscillator with high frequency stability for RFID

A low-power relaxation oscillator with a high frequency stability is presented for radio frequency identification (RFID). This oscillator implements an improved self-biased and a comparator multiplexing techniques to reduce the power consumption and chip area. A capacitor resetting delay cancellation technique based on a two-phase operation and a proportional to absolute temperature (PTAT) current with an upward curvature versus the temperature are adopted to maintain the frequency stability. The oscillator is designed in a 65nm standard CMOS process and occupies a small area of 0.0216mm(2). The post-layout simulation results show that a frequency drift of 0.95% from 0.7 to 1.7V and a temperature stability of 27ppm/degrees C as the temperature varies from -40 to 85 degrees C at a typical working frequency of 1.92MHz. Under a supply voltage of 0.7V, the maximum power consumption is only 15.4W at -40 degrees C. At room temperature, the figure of merit (FOM1 and FOM2) are 8nW/kHz and 89.5dB, respectively, which makes it more efficient than relaxation oscillators reported to date.