A Low-complexity Image Compression Algorithm for Address-Event Representation (AER) PWM Image Sensors

In Pulse-Width Modulation (PWM) image sensors the incident light intensity is represented by the timing of pulses. Exceptionally high dynamic range (DR) and improved signal-to-noise-ratio (SNR) have been demonstrated for this class of image sensors. Unfortunately, their spatial resolution is limited by the need of an in-pixel memory to record the timing information. The AER protocol is an attractive method for removing this overhead, since pixel trigger events can be sent as address vectors, and in-pixel data memories are no longer required. Regrettably, the need to send address vectors can place an increased burden on the communication channel and will limit the array resolution, frame-rate, and image quality. In this paper, we present a low-complexity AER Block Compression (AERBC) algorithm which exploits the statistically ordered nature of AER pixel arrays. The address vector overhead can be dramatically reduced under this scheme. Only 0.0625 comparisons and 0.125 subtractions are performed for each pixel, and on average 30.82 dB PSNR can be achieved at 1.0 bit-per-pixel code rate. A general strategy is also developed here to optimize AERBC parameters so a balance between performance and hardware resources can be reached.