ANALYSIS AND DESIGN OF SINGLE ENDED SRAM CELL FOR LOW-POWER OPERATION

In current developments of semiconductor memory cell design specially designing of static random access memory cell is become a major critical issue, due to the fact that the process technology is scaling to newer node very rapidly and hence the transistor size reduces most frequently. This paper analyzes the performance of a single ended SRAM cell for low power operation. As per the state of the art the single ended SRAM cell should operate at lowest power supply as possible so the presented design uses a single bit line for the read as well as writes operation of the cell which reduces the power requirements for the proper operation of the cell. This type of operation also improves the read stability and writes ability of the cell which overall improves the stability of the cell which is a critical factor for the SRAM cell designing. The proposed design has the enhanced transistor models for efficient operation. The main objective of this work is to operate the SRAM cell with proper stability and with low voltage. The standard 90nm processes technology is used in the modeling of transistors. The simulation result shows the low power operation of the cell with improved stability. The average transition power is obtained as 1.1 mu w with the power supply of 1.6v which shows the low power operation of the cell. Thus this work evaluates the performance of the single ended SRAM cell for low power operation with low voltage operation.