Fuzzy-based CMOS circuit partitioning in built-in current testing

被引：0

作者：

Tseng, WD ^{[1
]}

Wang, KC ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Comp & Informat Sci, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 1999年 / 7卷 / 01期

关键词：

CMOS; cost; partitioning; performance; test;

D O I：

10.1109/92.748207

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a fuzzy-based approach which pro,ides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus he determined to reflect a change of circuit properties.

引用

页码：116 / 120

页数：5

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