Time-Domain Modeling of All-Digital PLLs to Single-Event Upset Perturbations

被引:4
|
作者
Chen, Y. P. [1 ]
Massengill, L. W. [1 ]
Sternberg, A. L. [1 ]
Zhang, E. X. [1 ]
Kauppila, J. S. [1 ]
Yao, M. [2 ]
Amort, A. L. [2 ]
Bhuva, B. L. [1 ]
Holman, W. T. [1 ]
Loveless, T. D. [3 ]
机构
[1] Vanderbilt Univ, 221 Kirkland Hall, Nashville, TN 37235 USA
[2] Boeing Co, Seattle, WA 98124 USA
[3] Univ Tennessee, Chattanooga, TN 37403 USA
关键词
Fault injection; phase-locked loop (PLL); single event (SE) modeling; single-event upset (SEU);
D O I
10.1109/TNS.2017.2772262
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A uniform technology-agnostic time-domain model for both linear and nonlinear all-digital phase-locked loops (ADPLLs) is presented. This time-domain model can be used for single-event upset (SEU)-induced perturbation time prediction and SEU sensitivity characterization of common ADPLL topologies. The model is validated against field-programmable gate array-based fault injection experiments and two photon absorption laser experimental results on three different types of designs. The model is applicable to rad-harden by design activities, failure mode predictions, and general ADPLL design optimizations.
引用
收藏
页码:311 / 317
页数:7
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