FPGA-based hardware architecture for neural networks: Binary radix vs. stochastic

被引：6

作者：

Nedjah, N ^{[1
]}

Mourelle, LD ^{[1
]}

机构：

[1] State Univ Rio Janeiro, Fac Engn, Dept Syst Engn & Computat, Rio De Janeiro, Brazil

来源：

16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/SBCCI.2003.1232815

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper is focused on hardware implementation of neural networks. This paper describes the characteristics of two architectures designed to implement feed-forward fully connected artificial neural networks: the first FPGA prototype is based on traditional adders and multipliers of binary inputs while the second takes advantage of stochastic representation of the inputs. The paper compares both prototypes using the time x area classic factor.

引用

页码：111 / 116

页数：6

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