Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

被引：16
|
作者：
Kushwaha, Pragya [1 ]
Krishna, K. Bala [1 ]
Agarwal, Harshit [1 ]
Khandelwal, Sourabh [2 ]
Duarte, Juan-Pablo [2 ]
Hu, Chenming [2 ]
Chauhan, Yogesh Singh [1 ]
机构：
[1] Indian Inst Technol, Dept Elect Engn, Nanolab, Kanpur 208016, Uttar Pradesh, India
[2] Univ Calif Berkeley, Elect Engn & Comp Sci, Berkeley, CA 94720 USA
来源：
MICROELECTRONICS JOURNAL | 2016年 / 56卷
关键词：
FDSOI transistor; Self-heating effect (SHE); BSIM-IMG; Compact model; SOI MOSFETS; COMPACT MODEL; EXTRACTION; TEMPERATURE; FREQUENCY; TRANSPORT;
D O I：
10.1016/j.mejo.2016.07.014
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (R-th). Further, R-th increases with reduction in channel length (L-g). In this paper, we have proposed a compact model for the geometry and temperature dependence of R-th in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors. (C) 2016 Elsevier Ltd. All rights reserved.
引用
收藏
页码：171 / 176
页数：6
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