A Processor Accelerator for Software Decoding of Reed-Solomon Codes

被引：1

作者：

Ito, Kazuhito ^{[1
]}

Nasu, Keisuke ^{[1
]}

机构：

[1] Saitama Univ, Dept Elect & Elect Syst, Saitama 3388570, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2012年 / E95A卷 / 05期

关键词：

error correction code; Reed-Solomon; accelerator; decoding; VLSI DESIGN; ARCHITECTURE; COMMUNICATION; ALGORITHM;

D O I：

10.1587/transfun.E95.A.884

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Decoding of Reed-Solomon (RS) codes requires many arithmetic operations in the Galois field. While the software decoding of RS codes has the advantage of its flexibility to support RS codes of variable parameters, the speed of the software decoding is slower than dedicated hardware RS decoders because arithmetic operations in the Galois field on an ordinary processor require many instruction steps. To achieve fast software decoding of RS codes, it is effective to accelerate Galois operations by both dedicated circuitry and parallel processing. In this paper, an accelerator is proposed which is attached to the base processor to speed up the software decoding of RS codes by parallel execution of Galois operations.

引用

页码：884 / 893

页数：10

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