Full Adder Design Using Hybrid CMOS-SET Parallel Architectures

Hybrid CMOS-SET architectures, which combine the merits of CMOS and SET (single-electron tunneling) devices, promise to be a practical implementation for nanometer-scale circuit design. In this work we propose two binary full adders using hybrid CMOS-SET parallel architectures, which take advantage of the Coulomb oscillation with SET devices in order to improve the circuit area, power consumption and temperature effect. We use the improved MIB compact models for SET devices and simulate hybrid CMOS-SET circuits in Cadence environment with all the circuit parameters specified. The results show that the designed circuits are able to work at room temperature with high current drivability and low power dissipation.