Fast Delayed Signal Cancellation based PLL for unbalanced grid conditions

被引:0
|
作者
Contreras, Camilo [1 ]
Guajardo, David [1 ]
Diaz, Matias [1 ]
Rojas, Felix [1 ]
Espinoza, Mauricio [2 ]
Cardenas, Roberto [3 ]
机构
[1] Univ Santiago Chile, Dept Elect Engn, Santiago, Chile
[2] Univ Costa Rica, Dept Elect Engn, San Jose, Costa Rica
[3] Univ Chile, Dept Elect Engn, Santiago, Chile
关键词
Phase Locked Loop; Double Synchronous Reference Frame; Double Second Order Generalized Integrator; Delayed Signal Cancellation; SYSTEM;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Frequency identification is one of the most critical issues for grid-connected power converters, especially when the grid is unbalanced or distorted. Therefore, this paper proposes a novel frequency estimator with fast convergence for balance and unbalanced grid-voltage faults. The proposed algorithm is based on a Phase Locked Loop (PLL), enhanced with a fast positive and negative sequence detector. Delayed Signal Cancellation methodology with fast convergence is investigated under single-phase and two-phase voltage dip. The effectiveness of the proposed PLL is validated using simulations and experimental results.
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页数:5
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