An integrated HW and SW Fault Injection environment for real-time systems

被引：12
|
作者：
Benso, A [1 ]
Rebaudengo, M [1 ]
Reorda, MS [1 ]
Civera, PL [1 ]
机构：
[1] Politecn Torino, Dipartimento Automat & Informat, I-10129 Turin, Italy
来源：
1998 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 1998年
关键词：
D O I：
10.1109/DFTVS.1998.732158
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a system suited to support the Fault Injection process for microprocessor-based embedded systems. The system exploits a low-cost hardware board to monitor the processor status, to activate the fault injection procedure, and to gather information about the fault-fi-ee system behavior required to implement a set of fault collapsing rules. The overall environment allows at-speed fault injection experiments with negligible intrusiveness in the target system, and can therefore be used to efficiently evaluate real-time systems dependability.
引用
收藏
页码：117 / 122
页数：6
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