ATPG for Delay Defects in Current Mode Threshold Logic Circuits

被引：1
|
作者：
Palaniswamy, Ashok Kumar [1 ,2 ]
Tragoudas, Spyros [2 ]
Haniotakis, Themistoklis [2 ]
机构：
[1] Synopsys Inc, Mountain View, CA 94043 USA
[2] Southern Illinois Univ, Dept Elect & Comp Engn, Carbondale, IL 62901 USA
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2016年 / 35卷 / 11期
基金：
美国国家科学基金会;
关键词：
Automatic test pattern generation (ATPG); binary decision diagram (BDD); delay testing; threshold logic gate (TLG);
D O I：
10.1109/TCAD.2016.2533863
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An automatic test pattern generation approach to detect delay defects in a circuit consisting of current mode threshold logic gates is introduced. Each generated pattern should excite the maximum propagation delay at the fault site. Manufactured weights may vary, and maximum delay is ensured by applying an appropriately generated set of patterns per fault. Experimental results show the efficiency of the proposed methods.
引用
收藏
页码：1903 / 1913
页数：11
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