Quality of Fault Injection Strategies on Hardware Accelerator

被引：0

作者：

Guinebert, Iban ^{[1
]}

Barrilado, Andres ^{[2
]}

Delmas, Kevin ^{[1
]}

Galtie, Franck ^{[2
]}

Pagetti, Claire ^{[1
]}

机构：

[1] Off Natl Etud & Rech Aerosp, 2 Ave Edouard Belin, F-31000 Toulouse, France

[2] NXP Semicond, 134 Ave Gen Eisenhower, F-31100 Toulouse, France

来源：

COMPUTER SAFETY, RELIABILITY, AND SECURITY, SAFECOMP 2022 | 2022年 / 13414卷

关键词：

Formal modelling of hardware; Failure modes; Fault injection; MODELS; ERROR;

D O I：

10.1007/978-3-031-14835-4_15

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Safety-critical systems require understanding and mitigating the behavior of processors in case of failures. In order to analyze and verify hardware architectures, intensive fault injection campaigns are made. This work focuses on assessing the quality of fault injection strategies. The idea is to identify all failure scenarios associated to a hardware accelerator and estimate the coverage associated to a strategy. We have applied the approach on a LENET5 streaming architecture accelerator.

引用

页码：222 / 236

页数：15

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