High-level Synthesized 2-D IDCT/IDST Implementation for HEVC Codecs on FPGA

被引：0

作者：

Viitamaki, Vili ^{[1
]}

Sjovall, Panu ^{[1
]}

Vanne, Jarno ^{[1
]}

Hamalainen, Timo D. ^{[1
]}

机构：

[1] Tampere Univ Technol, Lab Pervas Comp, Tampere, Finland

来源：

2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2017年

基金：

芬兰科学院;

关键词：

High Efficiency Video Coding (HEVC); Inverse discrete cosine transform (DCT); Inverse discrete sine transform (DST); High-level synthesis (HLS); Field-programmable gate array (FPGA); DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents efficient inverse discrete cosine transform (IDCT) and inverse discrete sine transform (IDST) implementations for High Efficiency Video Coding (HEVC). The proposal makes use of high-level synthesis (HLS) to implement a complete HEVC 2-D IDCT/IDST architecture directly from the C code of a well-known Even-Odd decomposition algorithm. The final architecture includes a 4-point IDCT/IDST unit for the smallest transform blocks (TB), an 8/16/32-point IDCT unit for the other TBs, and a transpose memory for intermediate results. On Arria II FPGA, it supports real-time (60 fps) HEVC decoding of up to 2160p format with 12.4 kALUTs and 344 DSP blocks. Compared with the other existing HLS approach, the proposed solution is almost 5 times faster and is able to utilize available FPGA resources better.

引用

页码：385 / 388

页数：4

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