Interconnect-Aware High-Level Design Methodologies for Low-Power VLSIs

被引：0

作者：

Kameyama, Michitaka ^{[1
]}

Hariyama, Masanori ^{[1
]}

机构：

[1] Tohoku Univ, Grad Sch Informat Sci, Dept Comp & Math Sci, Sendai, Miyagi 9808579, Japan

来源：

TOWARDS GREEN ICT | 2010年 / 9卷

关键词：

High-level synthesis; scheduling; memory allocation; functional-unit allocation; interconnection complexity; VOLTAGES;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents two interconnect-aware high-level optimization techniques. One is scheduling and FU allocation minimizing the total energy time and area constraints based on data-transfer patterns. The other is memory allocation minimizing the number of memory modules and FUs with a parallel access capability for image processing.

引用

页码：265 / 274

页数：10

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