On-line diagnosis of interconnect faults in FPGA-based systems

This paper presents an on-line diagnosis approach for locating the interconnect faults in field programmable gate arrays (FPGAs)-based systems. The diagnosis proposed approach consists of two phases. Phase one is locating the faulty tile through partitioning the FPGA-based system into self-checking tiles. The faulty tile can be detected concurrently with the normal system operation. This operation will be performed prior to scheduling and allocating the circuit. The proposed partitioning approach was applied on certain circuits as a case study, and has been implemented using Xilinx foundation CAD tool with FPGA chip XC4010. The simulation study proved that our partitioning scheme reduces the test complexity and produces lower overheads. Upon locating a faulty tile and by the aid of a proposed path-list file per tile created during the routing process, the second phase of the diagnosis approach is applied only on the utilized interconnection of that tile for locating the faulty wires and switches. Therefore, the diagnosis approach is considered to be simplified.