A design for testability study on a high performance automatic gain control circuit

被引：5

作者：

Lechner, A ^{[1
]}

Richardson, A ^{[1
]}

Hermes, B ^{[1
]}

Ohletz, M ^{[1
]}

机构：

[1] Univ Lancaster, Dept Engn, Lancaster LA1 4YR, England

来源：

16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1998年

关键词：

design-for-testability; mixed signal; test; integrated circuit; I-DDQ;

D O I：

10.1109/VTEST.1998.670893

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presented.

引用

页码：376 / 385

页数：10

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