A test pattern generation unit for memory NPSF built-in self test

被引：0

作者：

Chrisanthopoulos, A ^{[1
]}

Kamoulakos, G ^{[1
]}

Tsiatouhas, Y ^{[1
]}

Arapoyanni, A ^{[1
]}

机构：

[1] Integrated Syst Dev SA, Adv Silicon Solut Div, Athens 15233, Greece

来源：

ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II | 2000年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper we present the design of a deterministic Test Pattern Generation (TPG) unit which can be exploited in a Built-In Self-Test (BIST) scheme for memory Neighborhood Pattern Sensitive Fault (NPSF) testing. The proposed TPG generates the required 5-bit Eulerian sequence that is needed for memory Type-1 NPSF testing.

引用

页码：425 / 428

页数：4

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