SMT-Based Verification of Safety-Critical Embedded Control Software

被引:1
|
作者
Adhikary, Sunandan [1 ]
Gurung, Amit [2 ]
Thakkar, Jay [3 ]
Da Costa, Antonio Bruto [1 ]
Dey, Soumyajit [1 ]
Hazra, Aritra [1 ]
Dasgupta, Pallab [1 ]
机构
[1] Indian Inst Technol Kharagpur, Dept Comp Sci & Engn, Kharagpur 721302, W Bengal, India
[2] Martin Luther Christian Univ, Dept Comp Sci, Shillong 793006, Meghalaya, India
[3] Indian Inst Technol Gandhinagar, Ctr Creat Learning, Palaj 382355, India
关键词
delta-approximation; control software verification; sampled data systems;
D O I
10.1109/LES.2020.3035560
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A large fraction of bugs discovered in the design flow of embedded control software (ECS) arises from the control software's interaction with the plant it controls. Traditional formal analysis approaches using interleaved controller-plant reach-set analysis grossly overapproximate the reachable states and does not scale. In this letter, we examine a verification approach that considers a control system with the (possibly nonlinear) plant dynamics and mode switches specified along with the actual control software implementation. Given this input, we generate a bounded-time safety verification problem encoded as satisfiability modulo theories (SMTs) constraints. We leverage delta-decidability over Reals to achieve scalability while verifying the control software.
引用
收藏
页码:138 / 141
页数:4
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