A Computationally Efficient Harmonic Extraction Algorithm for Grid Applications

被引:5
|
作者
Jana, Saikat [1 ]
Srinivas, S. [1 ]
机构
[1] Indian Inst Technol Madras, Dept Elect Engn, Chennai 600036, Tamil Nadu, India
关键词
Harmonic analysis; Power harmonic filters; Phase locked loops; Data mining; Signal processing algorithms; Cutoff frequency; Power quality; FFT; locked amplifiers; SYSTEM;
D O I
10.1109/TPWRD.2021.3054554
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The ability of an algorithm to extract power quality parameters on a low-end digital controller with constrained resources and computational capacity can promote comprehensive adoption of power quality control and monitoring infrastructure because of reduced cost and thus improve operational ability in a microgrid or distribution grid and support more in-depth integration of renewable energy. Since conventional harmonic extraction for single-phase grid mostly operate on Fourier transform, lock-in amplifier and their derivative algorithms, they demand large memory and computational power which are available with high-end application-specific processors, digital signal processors (DSPs) and field programmable gate arrays (FPGAs). In this paper, a computationally efficient harmonic extraction algorithm is proposed, which can be implemented on commercially available microcontrollers with ease, without compromising accuracy. A detailed theoretical analysis of the proposed method, along with various simulation and the experimental results are presented. Workarounds for minor implementation issues on digital controllers are discussed as well.
引用
收藏
页码:146 / 154
页数:9
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