Test vector decomposition-based static compaction algorithms for combinational circuits

被引：41

作者：

El-Maleh, AH ^{[1
]}

Osais, YE ^{[1
]}

机构：

[1] King Fahd Univ Petr & Minerals, Dhahran 31261, Saudi Arabia

来源：

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | 2003年 / 8卷 / 04期

关键词：

theory; algorithms; static compaction; combinational circuits; taxonomy; test vector; decomposition; independent fault clustering; class-based clustering;

D O I：

10.1145/944027.944030

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and memory requirements for the tester. In this article, a new approach to static compaction for combinational circuits, referred to as test vector decomposition (TVD), is proposed. In addition, two new TVD based static compaction algorithms are presented. Experimental results for benchmark circuits demonstrate the effectiveness of the two new static compaction algorithms.

引用

页码：430 / 459

页数：30

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