FPGA-based Implementation of Sorting Networks in MMC applications

In this paper an implementation technique for Field Programmable Gate Array (FPGA) devices of two Sorting Networks (SNs) used for control of Modular Multilevel Converter (MMC) is presented. In such applications, the classical sorting algorithms are based on repetitive/recursive loops, and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance of the capacitor voltage balancing algorithm. The advantages and the main challenges of the Bitonic SN and Even-Odd SN in MMC applications are discussed. Moreover, in order to pre-evaluate the required resources and the execution time, equations are derived for both the proposed SNs and then a comparison is performed between them. The proposed equations are validated by comparing the real required resources with the estimated ones by using the Xilinx Vivado Design Suite tool. Finally, the operation of the proposed Bitonic SN is also tested in Vivado Simulator, achieving the sorted list of 8 elements in 18 clock cycles as expected.