A novel co-decoding scheme to reduce memory in MPEG-2 MP@ML decoder

被引:0
|
作者
Chimienti, A [1 ]
Lucenteforte, M [1 ]
Pau, D [1 ]
Sannino, R [1 ]
机构
[1] CNR, Ctr Studio Televis, I-10135 Turin, Italy
关键词
D O I
10.1109/ISSSE.1998.738080
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an encoding algorithm which allows a Main Profile Main Level MPEG-2 decoder to reduce the external dedicated memory. Typically, for most TV applications, a 16 Mbit SDRAM is needed, but using a new compression approach it is possible to reduce this amount of memory to less than 8 Mbits for PAL sequences. The REMPEG50 (REduced Memory MPEG decoder and 50 %frame compression) is a modified architecture of a MPEG-2 decoder that needs only one half of the external memory while keeping a full comparibility with the standard MPEG-2 decoder. When compared to a "pure" MPEC-2 decompression scheme [1], this shows a very good trade-off between loss of MPEG-2 quality over different bit rates and overall increased complexity.
引用
收藏
页码:272 / 277
页数:6
相关论文
共 41 条
  • [31] A Novel Real-Time MPEG-2 Video Watermarking Scheme in Copyright Protection
    Jiang, Xinghao
    Sun, Tanfeng
    Li, Jianhua
    Yun, Ye
    [J]. DIGITAL WATERMARKING, 2009, 5450 : 45 - 51
  • [32] Fast Huffman Decoding Algorithm by Multiple-Bit Length Search Scheme for MPEG-2/4 AAC
    Ho, Han-Chang
    Lei, Sheau-Fang
    [J]. 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 2844 - 2847
  • [33] A novel adaptive vector quantization method for memory reduction in MPEG-2 HDTV decoders
    Bruni, R
    Chimienti, A
    Lucenteforte, M
    Pau, D
    Sannino, R
    [J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 1998, 44 (03) : 537 - 544
  • [34] A high-performance memory storage architecture for MP@HL MPEG2 decoder chip
    Wu, Zhihua
    Luo, Rong
    Wang, Hui
    Yang, Huazhong
    [J]. ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 721 - 724
  • [35] Design of a novel synthesis filter for real-time MPEG-2 audio decoder implementation on a DSP chip
    Paik, WK
    Hwang, SY
    [J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 1999, 45 (04) : 1119 - 1129
  • [36] DSP implementation of real-time MPEG-2 audio decoder using novel synthesis filter bank
    Paik, WK
    Hwang, SY
    [J]. ELECTRONICS LETTERS, 1999, 35 (14) : 1128 - 1130
  • [37] Motion estimation motion compensation hardware architecture for a scene-adaptive algorithm on a single-chip MPEG2 MP@ML video encoder
    Nitta, K
    Minami, T
    Kondo, T
    Ogura, T
    [J]. VISUAL COMMUNICATIONS AND IMAGE PROCESSING '99, PARTS 1-2, 1998, 3653 : 874 - 882
  • [38] A modified MPEG-2 audio decoding scheme based on it's low-cost fast algorithm and efficient data scheduling
    Tsai, TH
    Chen, LG
    Chang, HC
    Huang, SC
    [J]. ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : D530 - D533
  • [39] A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme
    Ramachandran, S
    Srinivasan, S
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2002, 25 (9-10) : 449 - 457
  • [40] A single-chip MPEG2 MP@ML Video Encoder LSI including wide search range motion estimation (H+/-288, V+/-96) and many functions for consumer use
    Takashima, M
    Ogura, E
    Hiranaka, D
    Ishii, T
    Ishikawa, T
    [J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 1998, 44 (03) : 784 - 792