A study on fault-tolerant circuits using redundancy

被引：0

作者：

Han, J ^{[1
]}

Jonker, P ^{[1
]}

机构：

[1] Delft Univ Technol, Fac Sci Appl, Pattern Recognit Grp, Delft, Netherlands

来源：

VLSI'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON VLSI | 2003年

关键词：

reliability; fault-tolerance; redundant logic design; triplicated interwoven redundant (TIR) logic; triple modular redundancy (TMR);

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A triplicated interwoven redundant (TIR) logic for we with NAND logic is proposed and a fault injection simulation method is used to investigate the fault-tolerance of a TIR circuit as well as that of an equivalent triple modular redundant (TMR) circuit. The evaluation shows that the reliability of the TIR circuit obtained by simulations is comparable to that of the TMR circuit obtained by simulations; both are however significantly higher than the reliability obtained by a classical TMR model. The TIR technique could be used as a fault-tolerant solution for circuits and systems based on nanometre-scale electronics.

引用

页码：65 / 69

页数：5

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