Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators

An efficient and reliable Multi-Level Cell (MLC) Spin-Transfer Torque Random Access Memory (STT-RAM) is proposed based on a Drop-And-Rearrange Approach, called DARA. Since CNN models are rather robust, less important bits are dropped, allowing important bits to be written in safe and reliable Single-Level Cell mode. Also, bits are rearranged to make the representation better aligned with memory cell characteristics. Bits with higher impact on the features value are stored in safer bit positions reducing the chance of read/write circuits to malfunction. Experimental results show that our approach provides comparable to error-free scenario reliability level, while doubling the bandwidth and maintaining error rate of less than 0.02 percent.