Fault Tolerant Routing Implementation Mechanism for irregular 2D Mesh NoCs

Network-on-Chip (NoC) is one of the promising communication architecture to provide scalability for many core designs. However, deep sub-micron technology related effects impact NoC reliability. Hence under this condition NoC must continue to provide at-least a path between each pair of its components as long as path is available. In this paper we propose fault tolerant routing implementation solution, targeting the implementation of any distributed routing algorithm for regular as well as irregular 2D meshes generated due to failures. The proposed approach is logic based and does not use any routing table to implement a routing algorithm. Experimental results show that proposed method provides 14% reduction in area when compared with existing logic based on-chip fault tolerant implementations. Further, proposed approach degrades performance gracefully while preserving 100% coverage to all irregular topologies generated from 2D mesh.