A Design Procedure for Sizing Comparators in Active Rectifiers using gm/ID Technique

被引：3

作者：

Ballo, Andrea ^{[1
]}

Grasso, Alfio Dario ^{[1
]}

Privitera, Marco ^{[1
]}

机构：

[1] Univ Catania, Dept Elect Elect & Comp Sci Engn DIEEI, Viale Andrea Doria 6, I-95125 Catania, Italy

来源：

2022 35TH SBC/SBMICRO/IEEE/ACM SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2022) | 2022年

关键词：

Active Rectifiers; Common-Gate Comparators; Energy Harvesting; g(m)/I-D; PCE; CMOS; METHODOLOGY; CIRCUIT;

D O I：

10.1109/SBCCI55532.2022.9893249

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper introduces a design strategy for common-gate comparators, as the widely implemented comparators in active rectification systems. The method is based on the g(m)/I-D technique and it embraces both the power conversion efficiency of the whole system and large signal performance parameters, such as the slew-rate. As an example, the proposed strategy has been adopted to design the comparator in a power management integrated circuit for energy harvesting in fully battery-less implantable medical devices. The overall performances of the rectifier are shown, giving out a post-layout power conversion efficiency higher than 92.5%.

引用

页数：6

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